1. Field of the Invention
The present invention relates to data transfer through a communication system channel, and, more particularly, to detection of data information from a recording medium.
2. Description of the Related Art
A read channel component is an integrated circuit (IC) of a computer hard disk (HD) drive that encodes, detects, and decodes data, enabling a read/write head to correctly i) write data to the disk drive and ii) read back the data. The disks in an HD drive have a number of tracks, each track consisting of i) user (or “read”) data sectors and ii) control (or “servo”) data sectors embedded between the read sectors. Information stored in the servo sectors is employed to position the head (e.g., a magnetic recording/playback head) over a track so that the information stored in the read sectors can be retrieved properly.
Referring to FIG. 1, a servo sector 100 typically comprises a servo preamble 101, followed by an encoded servo address mark (SAM) 102, followed by encoded Gray data 103, followed by a burst demodulation (demod) field 104, followed by a repeatable run-out (RRO) field 105. The servo preamble enables timing recovery and gain adjustment of the written servo data. The SAM is an identifier of fixed bit-length that identifies the beginning of the servo data, with the value for this identifier being the same for all servo sectors. For some prior-art systems, a 9-bit SAM is written (after encoding) between the servo preamble field and the servo Gray data.
Gray data represents the track number/cylinder information and provides coarse positioning information for the head. The burst demod field provides fine positioning information for the head. RRO field data provides head positioning information that is i) finer than that provided by Gray data and ii) coarser than that provided by the burst demodulation fields. Specifically, RRO field data is typically employed for compensation when the head does not follow a circular track around the disk.
A read sector comprises a read preamble, a read address mark (RAM), and encoded user data. The read preamble also provides for timing recovery and gain adjustment, and the RAM identifies the read sector user data.
Servo information is encoded by one or more encoders, each encoder converting M input bits (an input data block) into N output symbols (an output codeword). The encoded servo information is written to the disk and read back by a magnetic recording head. When the head of a recording system reads data from a sector of a hard disk, the data is provided as an analog signal (readback signal) that is subsequently level-adjusted, equalized, and sampled for further digital signal processing to detect and decode the servo information.
The readback data is equalized to a desired target partial response by an equalizer configured as a continuous time filter (CTF) followed by a discrete-time finite impulse response (FIR) filter. In a synchronous system, the sampling of the CTF output signal uses timing information generated by a digital phase-locked loop (DPLL) locked to the symbol rate (T). The output samples of the equalizer are quantized to digital sample values (‘Y’ values) using an A/D converter (ADC). The ‘Y’ values are applied to a data detector (e.g., threshold detector or Viterbi detector). A SAM detector then searches for the SAM bit pattern in the detected data. Once SAM is detected, the Gray code decoder decodes the data following the SAM data as Gray data. The burst demodulation is timed with respect to the detected SAM data based on known lengths of the SAM and Gray data. The detected SAM data thus serves as a reference for timing of the burst demodulation operation. Those lengths are, in some prior-art systems, a multiple of 4T.
A prior-art SAM detector for detecting an L-bit SAM operates is illustrated in FIG. 2. Every 4T (at the codeword boundary), the detected bit−(1 or 0) is shifted into L-bit shift register 201 (which is initialized to L Is before detection begins). Detected bits are denoted by d(.) in FIG. 1. The L bits in shift register 201 are then compared by L-bit comparator 203 with a copy of the L-bit pattern [s(1) s(2) . . . s(L)] used for the SAM, which is stored in register 202. If the bit patterns of shift register 201 and register 202 match, then SAM detection is declared. Otherwise, the detection and shifting process continues until the SAM is found.
As noted above, in a synchronous system, the SAM is detected using samples retimed with a recovered clock driven by a digital phase-locked loop. However, radial phase incoherence has been found to render SAM detection difficult in a synchronous system.